Flip chip technology is a method for coupling a chip (die) to a carrier, substrate or circuit board, wherein the die is electrically connected to the carrier without using bond wires. Solder bumps on the die surface disposed over the bond pads are used as bonding means, and the chip is then ‘flipped’ so that it is face down on the carrier. The solder bumps enable electrical coupling to traces in the carrier by means of capture pads and vias. An epoxy covering then ‘underfills’ the structure to absorb the stress. This technique allows for shorter interconnect lengths as well as more area available for routing.
In conventional technologies, the vias (which couple to electrical traces in the carrier) are filled in with conductive material. The resultant structure is usually not completely flat, such that a dimple is formed on the surface of the conductive material at the opening of the via. The top of the carrier is then plated to form capture pads over each via, where each capture pad is designed to have a similar diameter to the solder bumps on the die. The plating follows the contours of the filled-in via, such that the capture pad also has a dimpled surface, allowing the solder bump to sit in the dimple.
Newer technologies replace the solder bumps with copper (Cu) pillars/columns having a small solder bump at one end for contacting the capture pad. Please refer to FIG. 1A, which shows a diagram of a conventional die package 100 using solder bumps 73 to couple to vias 41, and FIG. 1B, which shows a conventional die package 150 using copper (Cu) columns 81 to couple to vias 41. In both diagrams, the same numerals are used to denote the same components.
FIG. 1A shows a die package 100, comprising a die 112, which has a plurality of bond pads 28 on its surface, each bond pad 28 having a solder bump 73 formed thereon. As shown in the diagram, the die 112 is flipped to couple to a carrier 114 by means of the solder bumps 73. The carrier 114 has a plurality of capture pads 34 on its surface, each capture pad 34 being formed over a via 41. The vias 41 couple to electrical traces (not shown) in the carrier 114. The vias 41 are filled with conductive material, represented by the diagonal lines.
FIG. 1B shows a die package 150, comprising the die 112, flipped to couple to the carrier 114. The bond pads 28 have copper columns 81 formed thereon rather than solder bumps, for coupling the die 112 to the carrier 114. As shown in the diagram, the copper columns 81 have a smaller diameter than the solder bumps 73 in FIG. 1A. In addition, each copper column 81 has a solder bump 93 formed at its end, the solder bumps 93 being of a similar diameter to the copper columns 81. The vias 41 are filled in with conductive material, as in FIG. 1A. The capture pads 54 in FIG. 1B are of a smaller diameter than the capture pads 34 in FIG. 1A, corresponding to the smaller diameter of the copper columns 81.
As illustrated in the two diagrams, the capture pads 34, 54 are formed to have a similar diameter to the connecting solder bumps 73 and 93, respectively. When Copper columns 81 are utilized, their smaller diameter as compared to the conventional solder bumps 73 means the capture pads 54 can be formed with a similarly smaller diameter; the use of Copper columns 81 can therefore free up the bonding area. The smaller diameter solder bump 93, however, has the disadvantage of having poor bonding contact with the plated capture pad 54; in particular, due to the presence of the dimple. Increasing the diameter of the Copper columns 81 can improve the bump-dimple contact, but this involves increasing the cap size, which is not desirable, and also negates the increased bonding area advantage.